Wang Song-Wen; Guo Hong-Xia; Ma Teng; Lei Zhi-Feng; Ma Wu-Ying; Zhong Xiang-Li; Zhang Hong; Lu Xiao-Jie; Li Ji-Fang; Fang Jun-Lin; Zeng Tian-Xiang

doi:10.7498/aps.73.20241365

Abstract

In this paper, graphene field effect transistors (GFETs) with the top-gate structure are taken as the research object. The electrical stress reliabilities are studied under different bias voltage conditions. The electrical pressure conditions are gate electrical stress (V_G = –10 V, V_D = 0 V, and V_S = 0 V), drain electric stress (V_D = –10 V, V_G = 0 V, and V_S = 0 V), and electrical stresses applied simultaneously by gate voltage and drain voltage (V_G = –10 V, V_D = –10 V, V_S = 0 V). Using a semiconductor parameter analyzer, the transfer characteristic curves of GFETs before and after electrical stress are obtained. At the same time, the carrier migration and the Dirac voltage V_Dirac degradation are extracted from the transfer characteristic curves. The test results show that under different electrical pressures, the carrier mobility of GFETs degrades continuously with the increase of electric stress time. Different electrical pressure conditions have varying effects on the drift direction and degradation of V_Dirac: gate electrical stress and drain electrical stress cause V_Dirac drift of the device in opposite directions, and the gate electrical stress is greater than the electrical stress applied by both gate voltage and drain voltage, leading to V_Dirac degradation of GFETs. An analysis of the causes indicates that different electrical stresses produce different electric field directions in the device, which can affect the carrier concentration and movement direction. Electrons and holes in the channel are induced and tunnel into the oxide layer, and they are captured by trap charges in the oxide layer and at the interface between graphene and oxide, forming oxide trap charges and interface trap charges. This is the main reason for reducing carrier mobility of GFET. Different electric field directions under different electric stresses produce positively charged trap charges and negatively charged trap charges. The difference in the type of trap charge banding is the main reason for the different directions of V_Dirac drift in GFETs. When both trap charges coexist, they have a canceling effect on the V_Diracdrift of the GFETs. Finally, by combining TCAD simulation the simulation model of the influence of electrical stress induced trap charge on the V_Dirac generation of GFET is further revealed. The result demonstrates that the differences in the type of trap charge banding have different degradation effects on the V_Dirac of GFETs. The related research provides data and theoretical support for putting graphene devices into practical application.

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Corresponding author: Guo Hong-Xia, guohongxia@nint.ac.cn

Funds: Project supported by the National Natural Science Foundation of China (Grant Nos. 12275230, 12027813).

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偏置电压条件	电应力测试时间点	转移特性曲线测试条件
栅极电应力(V_G = –10 V, V_D = 0 V, V_S = 0 V)	0 s, 100 s, 300 s, 500 s, 1000 s	V_G 从–5 V扫到5 V, V_D 为20 mV, V_S 接地
漏极电应力 (V_G = 0 V, V_D = –10 V, V_S = 0 V)
栅极电压与漏极电压同时施加的电应力 (V_D = –10 V, V_D = –10 V, V_S = 0 V)

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Vol. 73, Issue 23 - 2024-12-05

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