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Abstract

A neuromorphic chip is an emerging AI chip. The neuromorphic chip is based on non-Von Neumann architecture, and it simulates the structure and working principle of the human brain. Compared with non-Von Neumann architecture AI chips, the neuromorphic chips have significant improvement of efficiency and energy consumption advantages. The 3D-NAND flash memory has the merits of a mature process and ultra-high storage density, and recently it attracted many researchers’ attention. However, owing to the proprietary nature of the technology, there are few hardware implementations. This paper reviews the present research status of neuromorphic computing by using the 3D-NAND flash memory, introduces the forward propagation and backward propagation schemes, and proposes several improvements on the device, structure, and architecture of 3D NAND for neuromorphic computing.

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Corresponding author:Yang Dao-Hong,alan_yang@xmcwh.com

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Cited By

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	新型存储器					主流存储器
	PCM	ReRAM	STT-MRAM	FeRAM	FeFET	NOR flash	NAND flash
器件结构	1T-1R	1T-1R	1T-1R	1T-1C/ 1T-1FTJ	1T	1T	1T
器件面积F²	4—40	6—26	9—75	30—40	10—30	10	4
工艺节点/nm	14^[8,9]	14^[10]	22^[11]	130^[12]	22^[13]	40	15(2D) 80(3D)^[14]
芯片容量	16—64 GB (Intel optane)	1 MB— 32 GB^[10,15]	16 kB— 4 GB^[16,17]	16 kB— 128 MB^[18,19]	64 kB— 32 MB^[13,20]	1 MB—2 GB (Micron/Infineon/Macro- nix product manuals)	1 TB^[21]
写电压/V	< 3	< 1	< 2	< 3	～1.5	10—15	15—25
写时间/ns	75^[9]	1—10^[22]	3—14^[23,24]	1—10^[25]	1—10^[25]	10000^[26]	100000^[27]
写功耗/(pJ·bit^–1)	1^[28]	～10^[29]	4.5^[30]	0.1^[25]	1—10 fJ^[25]	49^[26]	～1000^[31]
读时间	12—130 ns^[8,32]	2.9—21 ns^[33,34]	2—26 ns^[30,35]	1—25 ns	1—10 ns	11 ns	3 μs^[27]
读功耗/(pJ·bit^–1)	2.47^[36]	1.76^[29]	0.7^[30]	9.8—19.2^[37]	0.27 fJ/bit^[38]	2.2^[26]	～100^[31]
开关比	> 10⁴	> 10³	> 2	> 2	> 10⁸	> 10⁸	> 10⁸
擦写次数	> 10^{10 [22]}	> 10¹²	> 10¹²	> 10¹²	10⁵—10⁹	< 10⁶	< 10⁵
保持时间/a	> 10	> 10	> 10	> 10	> 10	> 10	> 10
存储比特	2	6^[39]	1	3—4^[39]	2—3	2	4

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	文献工作
	[45]	[47]	[48]	[49]	[50]	[52]	[53]	[54]	[55]	[56]
技术节点	N.A.	N.A.	N.A.	N.A.	65 nm	N.A.	32 nm	N.A.	26 nm	26 nm
芯片容量	N.A.	N.A.	N.A.	64 GB	N.A.	N.A.	1.13 GB	N.A.	N.A.	N.A.
器件类型	N.A.	SLC	SLC	SLC	SLC	SLC	SLC	Analog	MLC	PLC
输入端口	位线	字线	漏端选通管的字线	位线	漏端选通管的字线	位线	位线	字线	位线	位线
输入编码	脉冲幅值	N.A.	二值编码	数字编码	数字编码	数字编码	数字编码	二值编码	脉宽编码	脉宽编码
输入信号精度	模拟	N.A.	1 bit	4 bit	8 bit	8 bit	8 bit	1 bit	模拟	模拟
突触精度	N.A.	1 bit	1 bit	4 bit	8 bit	8 bit	8 bit	N.A.	4 bit/2 bit	6 bit
反向传播方式	另选转置的突触阵列, 误差信号在位线上输入	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A	N.A.	误差信号施加在源极选通管位线上
神经网络	3层全连接网络	N.A.	4层全连网络、 6层卷积 + 3层全连接	VGG16	LeNet-5	VGG-16	VGG-8	两层全连接网络	6层卷积 + 3层全连接	2—7层全连接网络
神经网络的突触数量	0.3 MB	N.A.	N.A.	138 MB	N.A.	N.A.	110 MB	27	N.A.	N.A.
数据集	MNIST	N.A.	MNIST, CIFAR-10	CIFAR-10	MNIST	N.A.	CIFAR-10	ZVN	CIFAR-10	MNIST
识别率	94.5%	N.A.	98.12%, 87.11%	90%	98.5%	N.A.	N.A.	N.A.	89.38% (4 bit 权重)、87.1% (2 bit权重)	95.65%
能效/ (TOPS·W^–1)	N.A.	N.A.	N.A.	～40	N.A.	0.3	12.95	N.A	N.A.	N.A.

DownLoad: CSV

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Vol. 71, Issue 21 - 2022-11-05

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