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Abstract

The cylindrical surrounding double-gate metal-oxide-semiconductor field-effect transistor (CSDG MOSFET) is formed by adding an internal control gate to the cylindrical surrounding-gate (CSG) MOSFET. The inner gate of CSDG MOSFET acts as a second gate for enhanced charge control. At present, the research of CSDG MOSFET structure is widely concerned. Compared with double-gate MOSFET, triple-gate MOSFET and CSG MOSFET, the CSDG MOSFET provides good controllability of the gate over the channel. Additionally, the device allows for higher volume inversion than CSG MOSFET, which leads to better output characteristics. In order to study the electrical characteristics of CSDG MOSFET, the potential model of CSDG MOSFET is obtained by solving the two-dimensional Poisson equation in cylindrical coordinates. The effects of gate dielectric, channel length and gate dielectric thickness on the surface potential and electric field of CSDG MOSFET are studied. Besides, the drain-source current model of CSDG MOSFET is established by integrating the inverse charge along the channel. The effects of gate dielectric and gate dielectric thickness on the transconductance of CSDG MOSFET are studied. In addition, the effects of the downscaling of device parameters on the transfer characteristics and transconductance of CSDG MOSFET are studied. The electrical characteristics of CSDG MOSFET are analyzed and discussed. The results show that the minimum surface potential along the channel of CSDG MOSFET decreases with the increase of gate dielectric constant of gate dielectric layer. The electric field along the channel and along the radius, drain-source current and transconductance of CSDG MOSFET increase as the gate dielectric constant increases. The threshold voltage of CSDG MOSFET decreases as the gate dielectric constant increases. Moreover, with the downscaling of device parameters, the transfer characteristics and transconductance of CSDG MOSFET decrease. The performance of CSDG MOSFET can be significantly improved by using high-k gate dielectrics.

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Corresponding author:Yao Ruo-He,phrhyao@scut.edu.cn

Funds:Project supported by the Key-Area Research and Development Program of Guangdong Province, China (Grant No. 2019B010143003) and the National Natural Science Foundation of China (Grant No. 61871195)

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参数	定义	数值
R₁/nm	内栅介质层与硅体接触处半径	4
R₂/nm	外栅介质层与硅体接触处半径	14
L/nm	栅长度	30
t_ox/nm	介质层厚度	2
N_a/cm^–3	沟道掺杂浓度	10¹⁷
ε₀/(F·cm^–1)	真空介电常数	8.854 × 10^–14
ε_ox	栅介质介电常数	ε₀, 3.9ε₀, 7ε₀, 12ε₀, 20ε₀
ε_si	硅介电常数	11.8ε₀

DownLoad: CSV

L/nm	R₁/nm	R₂/nm	t_ox/nm	t_Si/nm
3	0.714	1.43	0.285	0.714
5	1.25	2.5	0.5	1.25
7	1.67	3.33	0.667	1.67
10	2.5	5	1	2.5

DownLoad: CSV

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Vol. 70, Issue 15 - 2021-08-05

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