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Abstract

Based on the wide-spectrum neutron beam (covering thermal neutrons and E> 10 MeV neutrons, with maximum energy of 1.6 GeV) provided by the China Spallation Neutron Source (CSNS), this paper focuses on the single event effect study of 14 nm FinFET large-capacity SRAM and 65 nm planar process SRAM device, using combined techniques of irradiation experiment, reverse analysis, and Monte-Carlo neutron transport simulation. The aim is to reveal the effect of integrated circuit process changing on the sensitivity of neutron induced single-bit and multiple-bit upsets (MBU), and to analyze the inner mechanisms, including the distribution of secondary particles in the sensitive volume, the characteristics of deposited charges, etc. The results show that compared with the 65 nm device, single event upset (SEU) cross section of the 14 nm FinFET device, induced by E> 10 MeV neutrons, is reduced by about 40 times, while the MBU ratio increases from 2.2% to 7.6%, which is due to the reduction of sensitive volume size of the 14 nm FinFET device (80 nm × 30 nm × 45 nm), pitch, and critical charge (0.05 fC). The main forms of MBU are double-bit upset, triple-bit upset and quadruple-bit upset. Unlike the phenomenon that the 65 nm device is immune to thermal neutrons, the use of the ¹⁰B element near M0 in the 14 nm FinFET device causes it to present the thermal neutron sensitivity to a certain extent. The SEU cross section induced by thermal neutrons is about 4.8 times smaller than that induced by E> 10 MeV neutrons. Based on the device cross-section and memory area images obtained from the reverse analysis, a device model is established and neutron transport simulation based on Geant4 toolkit is carried out. The E> 10 MeV neutrons result in abundant secondary particle distribution in the sensitive volume of the device, covering n, p into even W. The neutron energy and presence or absence of the W plug near the sensitive volume have an importantinfluence on the type and probability of secondary particles in the sensitive volume. The analysis and calculations show that a large number of high- Zsecondary particles with long range and large LET values generated by high-energy neutrons in the sensitive volume of the device are the inducement of MBU, and SEUs mainly result from the contribution of light ions such as p, He, and Si.

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Corresponding author:Lei Zhi-Feng,leizf@ceprei.com

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编号	SRAM工艺	型号	容量	供电电压(core)/V	封装形式
1#	65 nm平面	CY7 C1663 KV18	8 Mb × 18	1.8	BGA, 非倒装
2#	14 nm FinFET	—	8 Mb × 16	0.8	BGA, 倒装

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器件	存储单元尺寸/ μm × μm	灵敏区尺寸/ μm × μm	灵敏区厚度/nm	重离子LET阈值/ MeV·cm²·mg^–1	临界电荷/fC
14 nm FinFET SRAM	0.37 × 0.18	0.08 × 0.03	45	0.1	0.05
65 nm SRAM	1.0 × 0.5	0.20 × 0.19	450	0.22^[18]	1^[19]

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Vol. 69, Issue 5 - 2020-03-05

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