The optimization of wire size has become a key technology for improving the chip system performance. Based on the influence of the wire size of interconnects on the delay, power, area and bandwidth, we propose an idea of optimal wire size based on multi-objective optimization method and obtain a multi-objective constrained analytical model by curve-fitting approach. The Hspice verification shows that the analytical model presented in this paper has a high precision and the average error is less than 5%. The algorithm is simple and can effectively compensate for deficiencies in application of quality factor approach and it can be applied to computer-aided design of nano-scale complementary metal-oxide semiconductor (CMOS) system chips.