Negative bias temperature instability (NBTI) is a p-channel metal-oxide-semiconductor (PMOS) degradation mechanism, which becomes one of the important reliability concerns. The NBTI drastically influences device performance and circuit lifetime. On the other hand, the circuit performance is also affected by the fabrication-induced process variation when the transistor size shrinks to a nanometer-scale. In the presence of the fabrication-induced random variations, the NBTI aging process and its influence on PMOS device become a random process. In this paper, the joint effects of NBTI and process variations on PMOS device are investigated. Firstly, the influence of process variation on NBTI aging is analyzed based on the reaction-diffusion (R-D) mechanism. The NBTI-induced PMOS threshold voltage degradation depends not only on stress time but also on fabrication-determined process parameters, such as the initial threshold voltage and oxide thickness. Then the statistical model is proposed to model NBTI-induced aging under process variation, which captures the threshold voltage variation and oxide thickness variation as random vectors with normal distributions. For 100-times Monte-Carlo simulation based on 65 nm technology, the voltage error and oxide thickness error of the PMOS device are obtained. Applying these process errors to the statistical model, the results show that mean value of threshold voltages is increased along the negative direction with the stress time going on under the process variation and NBTI effect interaction. Meanwhile the standard deviation of threshold voltage is reduced, which represents that the matching between those PMOS devices becomes better. The proposed statistical model accuracy is verified by R-D model theoretical solutions. The maximum relative error of the mean value and of the standard deviations for the threshold voltages degradation of the PMOS device are only 0.058% and 0.91% respectively in 104 s. The distribution characteristic of PMOS NBTI effect is more serious to analog circuit, because analog circuit is more sensitive to device mismatch. For current steering digital-to-analog converter (DAC), PMOS device is always adopted as current source due to its good isolating properties. The PMOS current source requires good matching, and mismatch error could cause circuit failure. To realize aging simulation on DAC circuit in Spectre environment, the above statistical NBTI model is realized by Verilog-ASM language as the subcircuit module to PMOS device. Finally, this module is applied to the current steering DAC. Considering the NBTI effect under process variations, the simulation results show that the DAC gain error is increased with the stress time going on, while its linearity error is gradually reduced.