In order to design the power devices with the low loss required for the power integrated circuits (PIC), a new folded silicon LDMOS with the folding step oxide layer (SOFLDMOS) is proposed in this paper for the first time. In this structure, the step oxide layer is covered on the folded silicon surface with a periodic distribution. The surface electric field is optimized to be uniform by introducing a new electric field peak due to the electric field modulation effect by the step oxide layer. The breakdown voltage is improved to solve the breakdown voltage limitation problem in FALDMOS. Obtained in virtue of the ISE simulation are the results that the silicon limit is broken by applying the effects of the electric field modulation, accumulation of majority carriers, and conductive silicon region multiplier in the proposed SOFLDMOS. The saturation current of the drain electron is increased by about 3.4 times compared with that of the conventional LDMOS. When the breakdown voltage is 62 V, an ultra-low specific on-resistance of 0.74 mΩ·cm2 is obtained, which is far less than 2.0 mΩ·cm2 in the conventional LDMOS with the same breakdown voltage. The low loss requirements is achieved for the PIC with the low voltage region by the proposed SOFLDMOS.