Limited by materials and process stability, the nano-scale IC manufacturing process is still based on the 193 nm light technology and the wavelength is larger than the feature size of layout, thus the induced interference and diffraction greatly reduce the resolution, which affect the quality of the chip. So the layout needs to be checked by the design-for-manufacturability (DfM) model before manufacturing. Traditional DfM models describe the process steps using physical models, and deduce the convolution kernels by decomposing the matrix in corresponding physical models, which are not only complicated but also hard to use; thus combined with the insufficiency of physical models, it is difficult to describe the process with thousands of parameters. This paper uses convolution form as the framework of DfM model, and deduces the relationship, represented as convolution kernels, between layout and contour by an optimization method. Every element in the convolution kernels is optimized based on the input and output data of the process and is also a dimension to describe the process. This model overcomes the disadvantages of the traditional model which needs confidential information such as process parameters, and it has more powerful capability to describe the process. Moreover, the model can contain the layout correction information, and describe the process from layout to contour. Experiment results for 65 nm process show that the model has an accuracy of 8 nm.