As the feature size of MOSFET scales beyond 45 nm, SiO2 as gate dielectric fails to meet the performance requirement because of the high gate oxide leakage current. It is necessary to replace SiO2 with high-k materials. However, high-k materials as gate dielectric have some limitations and are not expectedly compatible with the conventional structure, inducing new challenges such as bad interfacial quality, increased threshold voltage, mobility degradation, etc. In this paper we review the problems encountered in the introduction of high-k gate dielectric into planar devices and the solutions in terms of material, device structure and process integration. Some novel applications of high-k materials in new devices and the future trend are also reviewed.