Optimization of interconnect power and repeater area is an important issue in the design of nanometer CMOS ICs. Based on RLC delay model, the paper proposes a new optimal model to minimize power and area overhead with constraints of target delay and target bandwidth. The proposed model is verified at 90 nm, 65 nm and 45 nm CMOS technology. Experimental result shows that the proposed model can save an average power consumption of 46% and 61% and can save an average area of 65% and 83% at the expense of 1/3 and 1/2 bandwidth, respectively. The proposed optimal model can be used in computer-aided design for nanometer CMOS system-on-chip.