Based on the nanometer CMOS technology, a novel parallel RLC coupling interconnect analytic model is presented. Based on the function approach and reduced order techniques, an analyzable expression for the outlying terminal of the disturbed line is derived by the model in the off-angle step input signal. In the 90 nm and 65 nm CMOS process, the proposed RLC coupling interconnect analytic model enables to estimate the crosstalk voltage within 4% errors compared with Hspice simulation for various interconnect coupling size. The proposed analytic model can be applied to the design of nanometer SOC and optimizing the design for VLSIs.