Radiation-hardened embedded flash technology is widely used in aerospace field. The high voltage nMOSFET is the key device to be hardened as it is the most sensitive device to total ionizing dose (TID) effect. In this study, the shallow tench isolation (STI) sidewall implantation method is used to harden 5 V nMOSFET for 180 nm eFlash process. Through the study of the TID response of the device, two problems emerge in this hardening technology. Firstly, the hardening ions are implanted after STI trench etching, the doping profile is influenced by the following thermal process, resulting in lower doping concentration at STI edge. The device fails to work due to high leakage current after 1×10 ⁵rad (1 rad = 10 ^–2Gy) (Si) radiation. Secondly, the hardening ions that are implanted in drain region reduce the breakdown voltage of PN junction on the drain side. Device cannot satisfy the actual requirement in the circuit. To solve these problems, we propose a new device hardening method called partial channel ion implantation. Comparing with previous method, in order to reduce the doping redistribution effect, we adjust the hardening ion implantation to an extent after the oxidation of gate oxide. Moreover, an extra mask is introduced to determine the hardening implantation region to avoid ion implantation on the drain side of the device. Therefore, the drain breakdown voltage will not be influenced by hardening implantation. By using this new hardening technology for high voltage NMOS, the device can maintain the typical design of strip-type gate. The hardening method is compatible with general process technology and does not influence the electrical parameters of the device obviously. The results show that with the partial channel ion implantation method, the drain leakage of the device is kept at a pico-ampere level after 1.5×10 ⁵rad (Si) radiation. That is five orders of magnitude lower than that obtained by using previous STI implantation hardening technology.