Power consumption has been the major bottleneck in the development of integrated circuits with reduced critical dimensions and improved integrated level. Tunnel field effect transistor (TFET) has been investigated as one of the promising replacements for traditional metal oxide semiconductor field effect transistor (MOSFET), owing to the introduction of band to band tunneling (BTBT) mechanism based on which a smaller subthreshold slope is achieved. However, a thinner oxide layer and a shorter channel length in TFET may induce localization of high current density, high electrical field distribution, and generation of heat, which abate the probability to survive electrostatic discharge (ESD). Besides, the novel BTBT operating principles also present a challenge to TFET ESD protection design. In this paper transmission line pulse test method is adopted to analyze the working principle of conventional TFET at onset, holding, discharge, and second breakdown during an ESD event. Based on these a new TFET ESD device protection design is proposed and characterized with a deeply doped n+ pocket near the source region beneath the gate, which can make effective adjustments of contact potential barrier, reduce tunneling junction width, thus better ESD design windows are obtained.