To maintain and improve the manufacturing yield of integrated circuit becomes a research hot spot in optimized circuit design and manufacturing technology, with the expansion of the integrated circuit scale and shrinkage of devices feature sizes. In order to reduce the yield loss caused by redundancy material defect and missing material defect, choosing a preferentially optimizing net becomes an important subject in the process of layout optimization. Layout optimization is an effective way to increase integrated circuit yield which is based on the critical area diminution. In the paper presented is a new kind of short circuit and open circuit sensitivity model, which is net-based and not only reflects the size of the short critical area between the single net and the nets around it, but also possesses open critical area. Because this model is based on single net and includes the information about the surrounding net, the short critical area between the single net and the net around it and the open critical area of its own can be reduced at the same time. In this way, the efficiency of layout optimization is enhanced. According to the experimental results, this sensitivity model can be used to choose the position for optimization.